The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device of a multi-port structure having a RAM port for random access of memory cells and a SAM port for serial access.
A conventional semiconductor memory device of a multi-port structure is shown in FIG. 5. A memory cell array 61 is provided as a RAM port, which array has memory cells disposed in a matrix shape and is randomly accessible. A data register 63 is also provided as a SAM port, which register stores one row of data and is serially accessible.
The memory cell array 61 is divided into a lower level memory cell array 61a to be accessed by the most significant bit (MSB) "0" of a column address, and an upper level memory cell array 61b to be accessed by MSB "1" of a column address. The data register 63 is also divided into a lower level data register 63a and an upper level data register 63b. A data transfer gate 62a is provided for data transfer between the data register 63a and memory cell array 61a, and a data transfer gate 62b is provided for data transfer between the data register 63b and memory cell array 61b.
The connection between the data transfer gate 62a and data register 63a within a circuit portion A enclosed by a broken line is as shown in FIG. 6. A pair of bit lines 71a and 71a are connected to transistors 76 serving as the data transfer gate 62a. Each of the transistors 76 becomes conductive when a drive signal is applied to its gate via a signal line 75 connected thereto.
In a conventional device, a pair of bit lines 71a and 71a on the RAM port side is made in one-to-one correspondence with each data register 77 on the SAM port side. In the split transfer between the memory cell array 61 and data register 63 at upper and lower levels, data is transferred via the data transfer gate 62a between the memory cell array 61a and data register 63a, and via the data transfer gate 62b between the memory cell array 61b and data register 63b.
An active one of the data registers 63a and 63b which are alternately made active is used for the data transfer of the SAM port to an external circuit. Used in the data transfer between the SAM port and RAM port, therefore, is one of the data registers alternately placed in a standby state which is not now transferring data to an external circuit.
For this reason, if continuous data read/write is to be executed by using the data register 63 in the split transfer manner, it has been necessary to alternately access the lower and upper memory cell arrays 61a and 61b, and it has not been possible to continuously access only one of the memory cell arrays, i.e., to continuously access only one of the memory cell arrays 61a and 61b from the SAM port. If a frame buffer were to be constructed using such a RAM and SAM port, there arises a problem of some restriction in mapping between a display screen and the memory.